By Rajeev Balasubramonian, Norman Jouppi
A key determinant of total method functionality and gear dissipation is the cache hierarchy seeing that entry to off-chip reminiscence consumes many extra cycles and effort than on-chip accesses. additionally, multi-core processors are anticipated to put ever better bandwidth calls for at the reminiscence process. these types of matters make it vital to prevent off-chip reminiscence entry through enhancing the potency of the on-chip cache. destiny multi-core processors may have many huge cache banks attached by means of a community and shared via many cores. consequently, many very important difficulties needs to be solved: cache assets needs to be allotted throughout many cores, facts has to be positioned in cache banks which are close to the getting access to center, and an important information needs to be pointed out for retention. eventually, problems in scaling latest applied sciences require adapting to and exploiting new expertise constraints. The booklet makes an attempt a synthesis of contemporary cache learn that has considering options for multi-core processors. it really is a very good place to begin for early-stage graduate scholars, researchers, and practitioners who desire to comprehend the panorama of modern cache learn. The e-book is appropriate as a reference for complex machine structure sessions in addition to for knowledgeable researchers and VLSI engineers. desk of Contents: easy components of huge Cache layout / Organizing facts in CMP final point Caches / regulations Impacting Cache Hit premiums / Interconnection Networks inside of huge Caches / know-how / Concluding feedback
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Extra info for Multi-Core Cache Hierarchies (Synthesis Lectures on Computer Architecture)
If we employ page-to-bank mapping, the bank number bits are a subset of the page number bits. Thus, by assigning a virtual page to a physical page, the OS also determines the cache bank that the entire page gets mapped to, hence the term page-to-bank mapping. Such a mapping presents the option to leverage the OS to optimize data placement in a shared cache, instead of the hardware-intensive and complex D-NUCA policies. Adopting standard terminology, the bank number bits, that represent a subset of the page number bits, can be referred to as the page color.
We also discussed the basic mechanisms required for data mapping, movement, and search. Note that the work by Kim et al.  dealt exclusively with a NUCA design for a single-core processor. The papers discussed in this section attempt to develop solutions for data management in a NUCA cache that support multiple cores. We first discuss a few papers that are characterized by their use of complex search mechanisms but that allow great flexibility in terms of data placement and migration. We then discuss some limited work on LLC data replication.
When a block is replicated, the design very much resembles a private cache organization. Each core’s private tag array points to a nearby copy of the data block. Since the tag array stores the block in Shared state, a write to that block is preceded by an invalidation operation on the bus to get rid of other shared copies. 1. DATA MANAGEMENT FOR A LARGE SHARED NUCA CACHE 25 section of this book is because they allow multiple tag arrays to point to a single shared block in the data array (to not only simplify producer-consumer sharing but also boost capacity by avoiding replication at times).
Multi-Core Cache Hierarchies (Synthesis Lectures on Computer Architecture) by Rajeev Balasubramonian, Norman Jouppi